1. Field of the Invention
This invention relates to a semiconductor device having a connecting structure for connecting in parallel two conductive layers to decrease the resistance of wiring layers.
2. Description of the Prior Art
In prior semiconductor integrated circuit devices, metal layers, diffusion regions formed in a semiconductor substrate, polycrystalline silicon (poly-Si) layers, and so on have been used as a wiring means. But, poly-Si layers are often used in a semiconductor device having multiple conductive layers.
Especially, in a static RAM (Random Access Memory) with four transistors and two resistors per one bit cell, a first poly-Si layer is used as the gate electrodes of MOS transistors and as wiring between circuit elements, and a second poly-Si layer is used as resistors. The static RAM circuit is shown in FIG. 1. MOS transistors (1) and (2) operate as gate transferring signals and MOS transistors (3) and (4) construct a flip-flop circuit. The sources of transistors 3 and 4 are connected to ground terminal Vss. Resistors (5) and (6) are loads and are connected to power source Vcc. The gates of the transistors (1) and (2) are connected to the word line 7 and the sources thereof are respectively connected to data lines 8 and 9. The signals of the data lines 8 and 9 are inverse to each other.
In the prior structure of this device, the data lines 8 and 9 are made of aluminum and the word line 7 is made of poly-Si.
So the delay time of the address-decode signal increases and is often over the tolerance limit in a high-speed static RAM. The delay time of the address-decode signal is substantially determined by the RC product of the gate capacitance C of the transfer gates (1) and (2) and the resistive value R of the word line (7). As the gate capacitance is determined by the characteristic peculiar to the transistor, it is difficult to decrease the gate capacitance C. So, it is necessary to decrease the resistive value R of the word line 7 in order to decrease the delay time of the address-decode signal. A structure improving the fault is disclosed in commonly owned U.S. application Ser. No. 128,955 filed Mar. 10, 1980. But the second poly-Si layer in the application has a low resistance value, so that it cannot be used as a load resistor. So a third poly-Si layer must be formed thereover as a load resistor. In general, as a conductive layer is formed on an insulation layer laying over another conductive layer, the thickness of the layer between the first and third conductive layers increases unnecessarily and the contact holes to the first conductive layer will be formed later. Further, a difference of the layer level become larger, too, so the metal layer thereon is easily cut off at the stepped portion. So, this structure is not desirable in a densely constructed integrated circuit device.